Duo binary signaling cascades
Described herein is a multi-level to binary converter in which a cascade of differential limiting amplifiers are utilised for each signal path to provide both increased gain and increased bandwidth without having to trade one off against the other. Where the multi-level data is duobinary, cascaded amplifiers are coupled to a XOR logic gate.
In each path, a copy of the duobinary signal is level shifted using an adjustable threshold before amplification in an amplifier. The shifted and duo binary signaling cascades signal is then fed to another amplifier where it undergoes the same steps. The outputs from each path are fed to the XOR logic gate to generate the desired binary signal, corresponding to a decoded synchronized NRZ data stream.
This application claims priority to European Patent Application No. The disclosure relates to improvements in or relating to signal processing, and, in particular, to the transmission of duo binary signaling cascades speed data through electrical backplanes. Today's research strongly focuses in high-speed multi-level optical and electrical interconnects with particular focus on interconnects using partial response and multi-level modulation formats.
A multi-level signal is a signal having a period T and comprising n signal levels, n being equal to or greater than 3. A duobinary signal is a three-level signal whose waveform comprises two eyes, and a PAM-4 signal is a four-level signal whose waveform comprises three eyes.
The number of the signal levels of a pulse amplitude modulated PAM signal corresponds to the number of the discrete pulse amplitudes usually some power of two. For example, in a PAM-4 signal, there are 2 2 possible discrete pulse amplitudes and in a PAM-8 signal, there are 2 3 possible discrete pulse amplitudes. The reception of such a multi-level modulation signal involves decoding the signal value from a duo binary signaling cascades received signal. This may be realized by an analog to digital converter ADC which directly decodes the signal level into bit values.
However, circuit implementations of a high-speed ADC are characterized by high power consumption and limited analog bandwidth. Communication and Electronics, vol.
Inter-symbol interference is introduced in a controlled manner so that it can be subtracted out to recover the original values. EP-A describes a way of using the limited bandwidth of the backplane channel advantageously to transform the NRZ signal into a duobinary signal. The roll-off response of a backplane is also a low pass filter but one that is too steep.
This filter emphasizes the higher frequency components, and provides flattening of the group-delay response across the band. However, a high speed duobinary to binary data converter is required so as not to lose the increased speed. To reach these new higher data rates, the differential limiting amplifiers need to operate with bandwidths and gains which can be up to two times those currently employed. Typically, an increase in gain is usually obtained at the expense of a loss in bandwidth.
In examples disclosed herein, the present disclosure provides a method for signal processing which provides both an increase in gain and an increase in bandwidth without the corresponding tradeoff between increasing gain and decreasing bandwidth.
In accordance with one aspect of duo binary signaling cascades present disclosure, a method duo binary signaling cascades converting a multi-level signal comprising a plurality of levels of modulation into an output signal includes: In one example, duo binary signaling cascades c further comprises: By having level shifting and then amplification, the speed limitation of conventional differential limiting amplifier circuits no longer becomes an issue when demodulating a multi-level signal.
Moreover, each amplifier requires less gain, which enables a higher analog bandwidth for the amplifier circuits. This higher bandwidth of the amplifier circuits allows for an increased data rate. In one embodiment of the disclosure, a first level shifting amplifier is used to perform elements c1 and c2. In another embodiment, elements c1 and c2 are repeated at least once using at least one further level shifting amplifier. This embodiment helps to optimise or improve the gain and the available bandwidth.
The method may further comprise the step of tuning each duo binary signaling cascades shifting duo binary signaling cascades in accordance with a reference signal to adjust the amount of level shifting. This example helps to facilitate the adjustment of the amount of offset introduced into each modulation path to provide better distinction of the levels of the output signal.
In accordance with another aspect of the present disclosure, a converter for converting a multi-level signal comprising a plurality of levels of modulation to an output signal includes a demodulation path for each level of modulation; means for providing the multi-level signal for each demodulation path; at least one amplifier within each demodulation path for amplifying the multi-level signal; and at least one duo binary signaling cascades gate connected to each demodulation path for providing the output signal.
Each demodulation path may also comprise a cascade of amplifiers, at least one amplifier providing level shifting and amplification of the level shifted signal for optimising both bandwidth and gain for the output signal. By having at least one amplifier which provides level shifting and subsequent amplification, the output from each demodulation path may have increased gain and an increased bandwidth without having to suffer the trade-off as is usual with conventional systems.
In one embodiment, each level shifting amplifier shifts the multi-level signal to a zero level which relates to an eye opening corresponding to a level of the demodulation path. In another embodiment, each level shifting amplifier shifts the multi-level signal so that only a part of duo binary signaling cascades signal is available for amplification.
By shifting the signal this way, only the relevant part of the signal is made available for amplification. In the specific embodiment of a duobinary signal having two demodulation paths, for example, an upper path and a lower path, the signals in each of the upper and lower paths can be shifted so that only one part of each signal is available for amplification.
In a further embodiment, each level shifting amplifier compresses a part of the signal not available for amplification. This reduces the duo binary signaling cascades power required as parts of the signal not to be amplified in each duo binary signaling cascades path are compressed.
In one embodiment, each level shifting amplifier has a gain greater than 1. In another embodiment, each level shifting amplifier is tunable in accordance with a reference signal.
By tuning each level shifting amplifier, it is possible to adjust the amount by which the signal is shifted in each demodulation path and therefore the part of the signal which is amplified for output. For a better understanding of the present disclosure, reference will now be made, by way of example, to the accompanying drawings in which:.
The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The receiver comprises a wideband amplifiera wideband splitterfirst and second comparators andand a duo binary signaling cascades asynchronous XOR gate which outputs a decoded NRZ signal and feeds it afterwards to a D-FlipFlop with a clock The resulting decoded synchronized NRZ data stream is further processed within the chip.
An input duobinary signal, after amplification by the wide band amplifieris shown in an eye diagram at the top of FIG. The comparatorsmay be implemented with differential amplifiers. The upper and lower threshold voltages V 1 and V 2 respectively correspond to the upper and lower eye crossings, shown in the eye diagram The duobinary signal is divided into two identical signals by the wideband splitter A first signal follows an upper path and is applied to an inverting input of the first comparator A second signal follows a lower path and is applied to a non-inverting input of the second comparator Threshold voltage V 1 is applied to the non-inverting input of the first comparator whereas threshold voltage V 2 is applied to the inverting input of the second comparator A waveform for the lower path is illustrated.
It will be appreciated that the waveform not shown for the upper path is effectively the same as that for the lower path but inverted. Waveform corresponds to the duobinary signal after the wideband splitter The signal is then applied to the non-inverting input of the second comparator Waveform duo binary signaling cascades to the signal at the output of the second comparator For high data rates, the requirements on the bandwidth and the gain are more stringent.
As a trade-off between gain and bandwidth needs to be achieved for optimisation, a solution to increase the bandwidth without reducing the gain comprises using a cascade of differential amplifiers as described in U. A cascade of amplifiers comprises duo binary signaling cascades least 2 amplifiers mounted in series. In this manner, each differential limiting amplifier requires less gain, which enables a higher analog bandwidth for the amplifier circuit.
Depending on the total gain required, a cascade of duo binary signaling cascades or more differential amplifiers can be implemented.
Notably, an offset is introduced within an amplifier due to the unbalanced DC component of a signal. When a signal goes through a differential amplifier, the non-zero DC component of the signal introduces an offset which shifts the signal up or down to counteract the DC component in the differential signal.
A solution to this issue is to use a cascade of amplifiers with level shifting correction in each amplifier to compensate for the offset introduced by the amplifier, but also to shift the 0 signal level to the most suitable position. The level shifting stage in the amplifier shall be such that the 0 level of the duobinary signal after level shifting correction corresponds to the lower eye crossing or the V 1 threshold for the upper path and to the higher eye crossing or the V 2 threshold for the lower path.
The level shifting can be set manually or automatically by a feedback loop. The thresholds in the amplifier have now a new function within the amplifier: The design of such amplifiers is therefore different from the differential amplifiers used in the prior art. In one embodiment, the controlled and tunable level shifting is implemented inside the differential amplifier.
Referring now to FIG. The first two level shifting amplifiers in the corresponding paths are now referenced as and respectively, and replace the comparatorsof the circuit shown in FIG. As before, a duobinary signal is transmitted through a channel to a receiver to generate a binary NRZ signal The receiver comprises duo binary signaling cascades wideband amplifiera wideband splitterand a logic asynchronous XOR gate as described with reference to FIG.
In this case, apart from the replacement of comparatorswith level shifting amplifiers andthere is an addition of at least one further level shifting amplifierin the upper and lower paths respectively.
The output of duo binary signaling cascades level shifting amplifier is now the inverting input of the level shifting amplifier and the output of the level shifting amplifier is duo binary signaling cascades the non-inverting input of the level shifting amplifier The new voltage thresholds V 3 and V 4 are now respectively the non-inverting input of the level shifting amplifier and the inverting input of the level shifting amplifierwhich also corresponds to the upper and lower eye crossings of the related eye diagrams.
Waveform corresponds to the duobinary signal after the wideband splitter but before the first amplification in the level shifting amplifier Waveform is the duobinary signal after level shifting correction such that its 0 level corresponds to the lower eye crossing and to the V 2 level. Duo binary signaling cascades illustrates the duobinary signal after amplification in the level shifting amplifier The response of an amplifier is only linear in a small range around the zero level.
For higher voltage values, an amplifier will saturate to a value of V sat such that no duo binary signaling cascades amplification gain of zero is obtained after this value has been reached. This explains the shape of waveformwhere the upper eye is flattened due to the gain loss around the saturation value.
This waveform does not correspond to the desired shape. However, duo binary signaling cascades next stage will not only allow for a gain and bandwidth increase but the additional stage will also improve the shape of the signal. Waveform is obtained after the level shift correction where the 0 level of the signal now corresponds to the lower eye crossing and to the V 4 level. After the second amplification, waveform is obtained. This waveform corresponds to that of the desired NRZ signal containing a fully amplified lower part of the eye diagram and where the upper part of the eye diagram is shown as a duo binary signaling cascades line.
Waveform illustrates the signal after it has been combined in the XOR gate It will readily be appreciated that the waveforms for the upper path will be inverted duo binary signaling cascades that the shifting is performed downwards instead of upwards and that the lower part of the eye diagram is the equivalent of a solid line. The input signal is applied to duo binary signaling cascades input terminals of the amplifier indicated by region The level shifted input signal is observed at the intermediate terminals indicated by regionand the amplification is observed at the output terminals indicated by duo binary signaling cascades